Own verification planning, estimation, and execution tracking. Define and lead verification methodology and standards across multiple projects, coordinating activities across multiple sites. Lead verification at block & chip level with various high-speed I - Ps integrated like ODSP, D 2 D IP, Ser. Des XSR/ PAM 4, Integrated drivers/ TIA, and control functions. Review specifications, participate in design reviews, and influence architecture for testability and verification efficiency. Mentor and coach verification engineers, driving continuous improvement in technical skills and execution. Debug complex silicon and system-level issues during bring-up phases. Support post-silicon bring-up and optimize integration and performance. Minimum Qualifications. Bachelor’s degree in Electrical or Computer engineering and 15 years of ASIC Design Verification experience, or Master’s degree in Electrical Engineering or Computer Engineering and 12 years of ASIC Design Verification experience, or PhD in Electrical Engineering or Computer Engineering 7 years in ASIC Design Verification experience. Experience in System Verilog, UVM, and verification methodologies. Experience owning and delivering verification for large-scale SoCs or subsystems. Experience leading verification teams or projects. Experience in scripting and automation such as Python, Perl, TCL, or Shell Scripts. Preferred Qualifications. Experience with leading larger teams, with the ability to empower team members to successful outcomes. Strong experience with UVM (Universal Verification Methodology) for developing scalable, reusable, and coverage-driven verification environments. Expertise in verification of Ser. Des IP, D 2 D PHY IP, ODSP & integrated transceiver features, CPU sub-system & Protocols (Ethernet, UCIE, UAL, SPI/ I 2 C, etc.)Experience influencing design for testability and verification. Proven experience in troubleshooting and debugging. Experience with Formal Verification, hardware description languages (HD - Ls) such as Verilog/ System Verilog)Experience with emulation and prototyping platforms (Veloce, HAPS). Experience collaborating with architecture and design teams on verification strategy.