The Principal So. C architect is responsible for architecting the 1 P So. C and its building blocks based on use case requirements provided by the system architecture team and the definition of the silicon provided by the Device Product Manager (PM). Key job responsibilities. The SOC architect collaborates with the IP architects, the silicon design team and the silicon PM when deciding on the silicon architecture, to deliver the performance/power requirements (input from the system architect), different IP requirements and constraints (input from the IP architect) and area/cost/schedule (input from the Device PM and silicon design team). The So. C Architect is also the Chip Lead for the So. C working closely with Physical Design team to partition the silicon, design the interconnect based on BW and performance requirements and develop preliminary floor plan, clocking and power management based on estimates. During post silicon phase, the So. C architect is the first line of defense for issues arising from ATE or bugs identified from silicon validation. In depth knowledge of test, debug and manufacturability is a must as the principal So. C Architect will help tackle design marginality issues due to process variations and recommend voltage, temperature tradeoffs to improve yield and ensuring that the recommendations are within design specifications. The role also requires deep understanding not only of the So. C micro-architecture but also of all highspeed interfaces (DDR, USB, HDMI etc.) and is expected to provide guidance to the respective domain owners during development and debug. Key deliverable from the SOC architect is the So. C architecture spec, along with the sub-system architecture specs in collaboration with IP architects and design leads. A day in the life. The work of a SOC Architect at Lab 126 spans the full chip development lifecyclefrom defining specifications for new edge AI-powered multimedia SO - Cs to reviewing microarchitecture designs and testplans with cross-functional teams. On any given day, you might be crafting architectural specs for an upcoming chip or debugging complex issues with older SO - Cs during bring-up and validation, requiring seamless collaboration across product, design, verification, and validation teams. About the team. The SSG Silicon Development team is building 1 P Multi-Core Processor SO - Cs with Machine Learning capability, high speed memories and multimedia functions consisting of several key I - Ps including Display, ISP, ML engine and Security for Devices & Services Org on advanced processor technology nodes. These custom SO - Cs have the overarching goal to bring power efficient best-in-class technical advancements at a competitive price point. The current team has over 4 plus years of experience building silicon along with the SW stack to use them. Basic Qualifications. Master's degree in EE or related field 10 years of experience in SoCs and/or silicon development 2 years of experience in the domain listed above 2 years of experience in RTL design, synthesis and timing closure 2 years of D - Fx (Design for cost, test, manufacturing)Preferred Qualifications. PhD in Electronic Engineering or related field. Experience leading an So. C project as a lead architect from conception to launch and has experience in all aspects of So. C design, including front-end architecture development, RTL design and synthesis, RTL modeling and verification, power and performance, and manufacturing and qualification. Experience designing So. C interconnects for high throughput media blocksand CP - Us. Experience with ARM and x 86 ISA - Expertise in at least one of the following areas: video system architecture,audio DSPs, low power WiFi and BT, graphics and display engines. Familiarity with silicon manufacturing process, including siliconqualification. Familiarity with embedded software development and debugging.