Digital Architecture and Design: Architect and design digital blocks and subsystems of complex high-speed Ser. Des I - Cs, including Gigabit-speed serial interfaces and video and data routing solutions. Develop Next-Generation Technologies: Architect, develop, and actively contribute to next-generation Open. GMSL technologies, including the definition of new architectures and participation in the development of Open. GMSL technical standards for future product generations. Specification Ownership: Write detailed block and subsystem-level specifications for design and implementation. RTL Design and Implementation: Use Verilog and System. Verilog to design digital blocks, subsystems, and top-level designs. Verification and Coverage Closure: Develop block-level testbenches, verify block functionality, and collaborate with verification teams to achieve full-chip verification and coverage closure. Digital Backend: Perform block- and top-level linting, CDC analysis, and power analysis. Assist with synthesis constraints and timing closure. Mixed-Signal Integration: Communicate closely with mixed-signal designers and verification engineers to support mixed-signal simulations and real-number modeling across the analog/digital boundary. Documentation and Design Reviews: Prepare technical documentation and lead architecture, design, and peer reviews. Lab Evaluation and Debug: Support silicon bring-up, characterization, and debug activities. Cross-Functional Collaboration: Collaborate across analog, digital, verification, test, and product definition teams to define requirements, support production test development, and ensure successful product execution. Technical Leadership: Provide technical leadership for complex Ser. Des subsystems and products. Minimum Qualifications:MSEE or Equivalent: Master's degree in Electrical Engineering or equivalent with 5 years of relevant experience or PhD with 3 years of relevant experience. Digital Design: Experience designing and verifying complex digital systems using Verilog/ System. Verilog. System Architecture & Implementation: Demonstrated ability to architect and plan designs at the system level, translating high-level product concepts into robust design implementations. Communication Skills: Clear and concise written and verbal communication skills, with team working experience and a proactive approach to problem-solving. Ser. Des & Communications Expertise: Understanding of communication theory, high-speed Ser. Des transceiver architectures, and video/data transport. Design Trade-Offs & Physical Implementation: Solid understanding of digital and analog design trade-offs, with experience in timing analysis, power estimation, physical design, and DFT concepts. Lab & Silicon Debug Experience: Hands-on experience with silicon bring-up and debug. Preferred Qualifications:Ser. Des Standards and Protocols: Expertise in high-speed Ser. Des standards and protocols, including Ethernet, USB, PC - Ie, and/or video (Display. Port, CSI/ DSI, HDMI)Technical Standards Experience: Experience authoring Ser. Des technical standards and/or participating in industry standards committees. Behavioral Modeling: Experience with behavioral modeling, including verification of mixed-signal systems with behavioral modeling. Team Leadership: Experience leading teams and/or projects.