Develops the logic design, register transfer level (RTL) coding, and simulation for an So. C design and integrates logic of IP blocks and subsystems into a full chip So. C or discrete component design. Participates in the definition of architecture and microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Works with IP providers to integrate and validate I - Ps at the So. C level. Drives quality assurance compliance for smooth IP - So. C handoff. Intel's Data Center Group is looking for a highly motivated logic designer engineer to join a seasoned team in designing future generation Intel SO - Cs. Your responsibilities will include but not be limited to:Perform RTL coding that meets functional, area, power and timing goals. Ensure design passes quality checks including Lint, CDC, Low Power checks, etc. Work with architects to understand design requirements. Write detailed micro-architectural specifications. Work closely with verification team to bring up and debug design in simulation. Work closely with physical design team to ensure design is physically implementable. The ideal candidate should exhibit the following traits:Solid problem-solving skills and willingness to multitask. Excellent written and verbal communication skills. Willing to work in a dynamic and team-oriented environment. Excellent collaboration skills. Qualifications:You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualification: Bachelor's degree in Electrical/ Computer Engineering or related STEM field with 6 years or more relevant experience. Master's degree in Electrical/ Computer Engineering or related STEM field with 5 years or more relevant experience. Depending on the degree obtained above, the listed years of experience will need to be in the following areas:SOC or Subsystem RTL design and integration using Verilog/ System. Verilog, or:IP RTL design using Verilog/ System. Verilog. Preferred Qualifications:Experience with So. C flows for Reset, Power Management, Interrupts and Error Handling Job Type:Experienced Hire. Shift:Shift 1 (United States of America)Primary Location: US, California, Santa Clara.