Join Intel's AI Revolution Intel's AI So. C organization develops cutting-edge products powering a wide range of AI applications, from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role. Join us to shape the future of AI hardware. What You'll Do As an RTL Design Engineer, you'll develop logic design, register transfer level (RTL) coding, and simulation for So. C designs, integrating IP blocks and subsystems into full chip So. C or discrete component designs. You'll participate in defining architecture and microarchitecture features while performing quality checks across various logic design aspects from RTL to timing/power convergence. You'll apply strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals while ensuring design integrity for physical implementation. Working closely with verification teams, you'll review verification plans and resolve failing RTL tests to ensure feature correctness. You'll follow secure development practices and collaborate with IP providers for So. C-level integration and validation. Key Responsibilities. Architecture & Design - Contribute to evaluation of architectural trade-offs considering features, performance, and system constraints - Implement RTL in Verilog/ System Verilog based on defined micro-architecture - Integrate IP blocks at top level and ensure synthesis- and timing-clean design. Verification & Validation - Work closely with verification teams to achieve full coverage and robust validation - Develop timing constraints for IP blocks and assist physical design teams with synthesis, timing closure, and formal equivalence checks - Support silicon bring-up and post-silicon validation activities, including debug and performance analysis. Collaboration & Quality - Collaborate with senior engineers to adopt best practices and improve design methodologies - Drive quality assurance compliance for smooth IP/ So. C handoff - Work with IP providers to integrate and validate I - Ps at the So. C level. Qualifications:Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications - Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science 4 years of experience in/with:RTL design and implementation for ASIC/ So. C development Proficiency in Verilog/ System Verilog for RTL coding and design. Experience with synthesis tools and timing closure methodologies. Preferred Qualifications Understanding of clock domain crossings, power optimization, and timing closure. Exposure to So. C system integration and CPU subsystem design. Familiarity with standard bus protocols (AXI, AHB, etc.) and embedded processor architectures. Knowledge of high-speed and low-power design techniques. Experience with static timing analysis (STA) tools and methodologies. Hands-on experience with formal verification tools and techniques. Basic scripting skills (Python, TCL, etc.) for automation. Experience with EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools. Ability to work in a dynamic environment and adapt to changing requirements. Strong problem-solving skills, collaborative mindset, and eagerness to learn Job Type:Experienced Hire. Shift:Shift 1 (United States of America)Primary Location: US, California, Folsom.